Last year, Intel confirmed that Xe-HPC is based on Foveros CO-EMIB packaging technology, as the processor itself
The base tile is made using Intel's 10nm SuperFin architecture, but Rambo Cache Tile, for example, already uses10nm Architecture in Enhanced SuperFin.Computational tiles are fabricated using external and Next-Gen nodes, while Xe I/O tiles are made exclusively using an external foundry.
The GPU is supposed to be Xe-HPChas 8 processing cores on two tiles, but it is currently unknown how many execution units each tile can hold. The last official photo shows four stacks of HBM for each of the two matrices.
Xe-HPC is ready to be turned on, which means that the chip is alreadyactivated by Intel labs and is currently undergoing testing. Intel Xe-HPC is expected to debut next-generation Xeon processors based on Sapphire Rapids architecture.
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